J. Tom Pawlowski
Chief Technologist, Micron

As Chief Technologist of the Micron Innovation Team, J. Thomas Pawlowski is responsible for determining and defining innovative products which expand the breadth of Micron's product offering. During his tenure at Micron, Thomas has been responsible for memory architecture and product definition in networking, communications, PC and server applications including products built on SRAM, DRAM and FLASH processes.  Thomas has created or co-created the following DRAM and SRAM devices: reduced latency DRAM II (RLDRAM(tm) II); pipelined, burst, synchronous SRAM (used in Pentium® and PowerPC® systems); Zero Bus Turnaround(tm) (ZBT®) SRAM (used in network and communication systems); double data rate (DDR) SRAM; and Quad Data Rate(tm) (QDR(tm)) SRAM (versions I, II, and III) and other products yet to be released. Thomas holds over 80 U.S. and international patents with more pending.

Prior to joining Micron in 1992, Thomas worked for eight years at Allied Signal Aerospace. He holds a bachelor of applied science degree in electrical engineering from the University of Waterloo, Canada.